This invention relates to metallization of integrated circuitry and more particularly to an additive metallization process in which interconnect lines are formed of a conductive metal, such as gold, over a semiconductor substrate surface with an intervening layer of a barrier metal.
Additive integrated circuit metallization processes are known to have a number of advantages over conventional substractive metallization techniques, and particularly in forming interconnects of a corrosion and oxidation resistant metal, such as gold.
A known gold IC metallization process is disclosed in U.S. Pat. No. 4,687,552 to Early et al, and references cited therein. Briefly, such a process commences by depositing a barrier metal layer, such as tungsten or a titanium tungsten (TiW), over a surface of a semiconductor substrate, followed by deposition of a thin plating layer, such as palladium. These layers may be deposited in a substantially flat layer directly onto the semiconductor substrate surface or, as shown in Early et al, over an insulative layer that has been patterned to provide contact openings in which portions of the semiconductor substrate surface are exposed. Next, a positive photoresist layer is applied and patterned to expose an area of the circuit upon which the metal interconnect is to be formed. Interconnect metal, such as gold, is then electroplated upon the exposed surface regions of the plating metal to form the metal interconnect lines. After removing the photoresist, the exposed areas of plating metal and barrier metal are etched away, using a conventional wet etch technique with the interconnect metal serving as a mask, to electrically isolate the interconnections. This forms a first-layer interconnect pattern. An insulative layer, such as silicon dioxide, can then be applied over the first-layer interconnections and the foregoing procedure can be repeated to form second layer interconnections. Third layer interconnections can be similarly formed.
The foregoing approach has a number of drawbacks. One is that the step of wet etching the plating and barrier metal layers tends to undercut the interconnect metal layers. Undercutting occurs because wet etching is essentially isotropic; thus, the barrier metal not masked by the interconnect metal is removed from a margin extending beneath the edges of the interconnect metal. Added problems include the facts that using palladium as a plating layer catalyzes the undercutting, and that, due to topographic variations, it is necessary to overetch by 20-25%. A second problem, for which Early et al describe and propose one solution, is deformation of the interconnect metal line profiles during subsequent process steps, particularly annealing. This problem is enhanced by the fact that electroplating the gold metal lines into a photoresist pattern produces a retrograde sidewall, which is accentuated by deformation due to heat treating.
Early et al approached the latter problem by deposition of a rhodium layer atop the gold interconnect layer. This approach requires the use of a second electrodeposition step, and, further, requires that the palladium layer be sputter etched, rather than wet etched, to avoid removing gold and undercutting the rhodium. Moreover, this approach does not avoid the undercutting affects of a wet TiW etch.
An alternative approach to the deformation problem is known as reverse anneal (RA). The RA approach is a modification of the conventional process wherein the metal anneal is performed before the wet etch of the field metal. In this technique, the major profile change of the metal lines during the annealling step occurs before the isotropic etch. This sequence moves the starting edge of the undercut outward to where the gold has relaxed. Unfortunately, annealling while Pd/TiW or TiW layers are still continuous between the gold metal lines leads to conductive paths or "stringers" between metal lines, apparently composed of Au+Pd material. Such stringers can cause unacceptable electrical leakage between lines and degrade the reliability of the circuit.
Accordingly, a need remains for a satisfactory additive metallization process, particularly one that is suitable for gold metallization with a barrier layer, for making conductive interconnections across a semiconductor substrate surface.